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quad channel, 128 - /256 - position, i 2 c/spi, nonvolatile digital potentiometer data sheet ad5124 / AD5144 / AD5144a rev. 0 document feedback information furnis hed by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject t o change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 analog devices, inc. all rights reserved. technical support www.analog.com features 10 k and 100 k resistance options resistor tolerance: 8% maximum wiper current: 6 ma low temperature coefficient: 35 ppm/c wide bandwidth: 3 mhz fast start - up time < 75 s linear gain setting mode single - and dual - supply operation indepen dent logic supply : 1.8 v to 5.5 v wide operating temperature : ? 40 c to +125c 4 mm 4 mm package option 4 kv esd protection applications portable electronics level adjustment lcd panel brightness and contrast control s programmable filters, delays, and t ime constants programmable power suppl ies functional block diagram v dd lrdac v ss gnd w p v logic 7/8 serial interface power-on reset rdac1 input register 1 rdac2 input register 2 rdac3 input register 3 rdac4 input register 4 eeprom memory a1 w1 b1 a2 w2 b2 a3 w3 b3 a4 w4 b4 ad5124/AD5144 sync/addr0 sclk/sc l sdi/sd a sdo/addr1 dis reset 10877-001 figure 1. ad5124 / AD5144 24 - l ead lfcsp general description the ad5124 / AD5144 / AD5144a potentiometers provide a nonvolatile solution for 128 - /256 - position adjustment applications , offering g uaranteed low resistor tolerance errors of 8% and up to 6 ma current density in the ax, bx, and wx pins. the low resistor tolerance and low nominal temperature coefficient simplify open - loop applications as well as applications requiring tolerance matchi ng. the linear gain setting mode allows independent programming of the resistance between the digital potentiometer terminals, through the r aw and r wb string resistors, allowing very accurate resistor matching. the high bandwidth and low total harmonic di stortion (thd) ensure optimal performance for ac signals, making these devices suitable for filter design. the low wiper resistance of only 40 ? at the ends of the resistor array allow for pin - to - pin connection. the wiper values can be set through an spi - /i 2 c - compatible digital interface that is also used to read back the wiper register and ee prom content s. the ad5124 / AD5144 / a d5144a are available in a compact , 24- lead, 4 mm 4 mm lfcsp and a 20- lead tssop. the parts are guaranteed to operate over the extended industrial temperature range of ?40c to +125c. table 1 . family models model channel position interface package ad5123 1 quad 128 i 2 c lfcsp ad5124 quad 128 spi /i 2 c lfcsp ad5124 quad 128 spi tssop ad5143 1 quad 256 i 2 c lfcsp AD5144 quad 256 spi/i 2 c lfcsp AD5144 quad 256 spi tssop AD5144a quad 256 i 2 c tssop ad5122 dual 128 spi lfcsp/tssop ad5122a dual 128 i 2 c lfcsp/tssop ad5142 dual 256 spi lfcsp/tssop ad5142a dual 256 i 2 c lfcsp/tssop ad5121 single 128 spi/i 2 c lfcsp ad5141 single 256 spi/i 2 c lfcsp 1 two potentiometers and two rheostats. www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagrams tssop ............................................ 3 specifications ..................................................................................... 4 electrical characteristics ad5124 .......................................... 4 electrical characteristics AD5144 and AD5144a ................ 7 inte rface timing specifications ................................................ 10 shift register and timing diagrams ....................................... 11 absolute maximum ratings .......................................................... 13 thermal resistance .................................................................... 13 esd caution ................................................................................ 13 pin configurations and function descriptions ......................... 14 typical performance characteristics ........................................... 17 test circuits ..................................................................................... 22 theory of operatio n ...................................................................... 23 rdac register and eeprom .................................................. 23 input shift register .................................................................... 23 serial data digital interface selection, dis ............................ 23 spi serial data interface ............................................................ 23 i 2 c serial data interface ............................................................ 25 i 2 c address .................................................................................. 25 advanced control modes ......................................................... 27 eeprom or rdac register protection ................................. 28 load rdac input register ( lrdac ) ..................................... 28 rdac architecture .................................................................... 31 pro gramming the variable resistor ......................................... 31 programming the potentiometer divider ............................... 32 terminal voltage operating range ......................................... 32 power - up sequence ................................................................... 32 layout and power supply biasing ............................................ 32 outline dimensions ....................................................................... 33 ordering guide .......................................................................... 34 revision history 10/ 12 rev ision 0: initial version www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ad5124/AD5144/AD5144a rev. 0 | page 3 of 36 functional block dia grams tssop v dd v ss gnd v logic 7/8 spi serial interface sdo sclk sdi power-on reset sync rdac 1 input register 1 rdac 2 input register 2 rdac 3 input register 3 rdac 4 input register 4 eeprom memory a1 w1 b1 a2 w2 b2 a3 w3 b3 a4 w4 b4 ad5124/AD5144 10877-002 figure 2. ad5124 / AD5144 20 - l ead tssop v dd v ss gnd v logic 8 i 2 c serial interface addr scl sda power-on reset reset rdac 1 input register 1 rdac 2 input register 2 rdac 3 input register 3 rdac 4 input register 4 eeprom memory a1 w1 b1 a2 w2 b2 a3 w3 b3 a4 w4 b4 AD5144a 10877-003 figure 3. AD5144a 20 - l ead tssop www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 4 of 36 specifications electrical character istic s ad5124 v dd = 2.3 v to 5.5 v , v ss = 0 v ; v dd = 2.25 v to 2.75 v , v ss = ?2.25 v to ?2.75 v; v logic = 1.8 v to 5.5 v, ?40c < t a < +125c, unless otherwise noted. table 2 . parameter sym bol test conditions/comments min typ 1 max unit dc characteristics rheostat mode (all rdacs) resolution n 7 bits resistor integral nonlinearity 2 r - inl r ab = 10 k ? v dd 2.7 v ? 1 0. 1 + 1 lsb v dd < 2.7 v ? 2.5 1 + 2.5 lsb r ab = 100 k ? v dd 2.7 v ? 0.5 0.1 + 0.5 lsb v dd < 2.7 v ? 1 0. 25 + 1 lsb resistor differential nonlinearity 2 r - dnl ? 0.5 0. 1 +0.5 lsb nominal resistor tolerance r ab /r ab ? 8 1 +8 % resistance temperature coef ficient 3 (r ab /r ab )/t 10 6 code = full scale 35 ppm/c wiper resistance 3 r w code = zero scale r ab = 10 k ? 55 125 ? r ab = 100 k ? 130 400 ? bottom scale or top scale r bs or r ts r ab = 10 k ? 40 80 ? r ab = 100 k ? 60 230 ? nominal resistance match r ab1 /r ab2 code = 0xff ? 1 0.2 +1 % dc characteristics potentiometer divider mode (all rdacs) integral nonlinearity 4 inl r ab = 10 k ? ? 0.5 0. 1 + 0.5 lsb r ab = 100 k ? ? 0. 25 0. 1 +0. 25 lsb differential nonlinearity 4 dnl ? 0. 25 0. 1 +0. 25 lsb full - scale error v wfse r ab = 10 k ? ? 1 .5 ? 0.1 lsb r ab = 100 k ? ? 0.5 0. 1 + 0.5 lsb zero - scale error v wzse r ab = 10 k ? 1 1.5 lsb r ab = 100 k ? 0. 25 0.5 lsb voltage divider temperature coefficient 3 (v w /v w )/t 10 6 code = half scale 5 ppm/c www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ad5124/AD5144/AD5144a rev. 0 | page 5 of 36 parameter sym bol test conditions/comments min typ 1 max unit resistor terminals maximum continuous current i a , i b , and i w r ab = 1 0 k ? ? 6 +6 ma r ab = 100 k ? ? 1.5 +1.5 ma terminal voltage range 5 v ss v dd v capacitance a, capacitance b 3 c a , c b f = 1 mhz, measured to gnd , code = half scale r ab = 10 k ? 25 pf r ab = 100 k ? 12 pf capacitance w 3 c w f = 1 mhz, measured to gnd, code = half scale r ab = 10 k ? 12 pf r ab = 100 k ? 5 pf common - mode leakage current 3 v a = v w = v b ? 500 15 + 500 na digital inputs input logic 3 high v inh v logic = 1.8 v to 2.3 v 0.8 v logic v v logic = 2.3 v to 5.5 v 0.7 v logic v low v inl 0.2 v logic v input hysteresis 3 v hyst 0.1 v logic v input current 3 i in 1 a input capacitance 3 c in 5 pf digital outputs output high v oltage 3 v oh r pull - up = 2.2 k ? to v logic v logic v output low voltage 3 v ol i sink = 3 ma 0.4 v i sink = 6 ma , v logic > 2.3 v 0.6 v three - state leakage current ? 1 +1 a three - state output capacitance 2 pf power supplies single - supply power range v ss = gnd 2.3 5.5 v dual - supply power range 2.25 2.75 v logic supply range single s upply, v ss = gnd 1.8 v dd v dual s upply, v ss < gnd 2.25 v dd v positive supply current i dd v ih = v logic or v il = gnd v dd = 5.5 v 0.7 5.5 a v dd = 2.3 v 400 na negative supply current i ss v ih = v logic or v il = gnd ? 5.5 ? 0.7 a ee prom store current 3 , 6 i dd_ee prom _store v ih = v logic or v il = gnd 2 ma ee prom read current 3 , 7 i dd_ee prom _read v ih = v logic or v il = gnd 320 a logic supply current i logic v ih = v logic or v il = gnd 1 120 na power dissipation 8 p diss v ih = v logic or v il = gnd 3.5 w power supply rejection ratio psr r ? v dd / ? v ss = v dd 10%, code = full scale ? 66 ? 60 db www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 6 of 36 parameter sym bol test conditions/comments min typ 1 max unit dynamic characteristics 9 bandw idth bw ? 3 db r ab = 10 k ? 3 mhz r ab = 100 k ? 0.43 mhz total harmonic distortion thd v dd /v ss = 2.5 v, v a = 1 v rms, v b = 0 v, f = 1 khz r ab = 10 k ? ? 80 db r ab = 100 k ? ? 90 db resistor noise density e n_wb code = half scale, t a = 25c, f = 10 khz r ab = 10 k ? 7 nv/hz r ab = 100 k ? 20 nv/hz v w settling time t s v a = 5 v, v b = 0 v, from zero scale to full scale, 0.5 lsb error band r ab = 10 k ? 2 s r ab = 100 k ? 12 s crosstalk (c w1 /c w2 ) c t r ab = 10 k ? 10 nv - sec r ab = 100 k ? 25 nv - sec analog crosstalk c ta ? 90 db endurance 10 t a = 25c 1 mcycles 100 kcycles data retention 11 50 years 1 typical values represent aver age readings at 25c, v dd = 5 v, v ss = 0 v, and v logic = 5 v. 2 resistor integral nonlinearity error (r - inl) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r - dnl measures the relativ e step change from ideal between successive tap positions. the maximum wiper current is limited to (0.7 v dd )/r ab . 3 guaranteed by design and characterization, not subject to production test. 4 inl and dnl are measured at v wb with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 r esistor t erminal a, r esistor t erminal b, and r esistor t erminal w have no limitations on polarity with respect to each other. dual - supply operation enables ground referenced bipolar signal adjustment . 6 different from operating current; supply current for eeprom program lasts approximately 30 ms. 7 different from operating current; supply current for eeprom read lasts approximately 20 s . 8 p diss is calculated from (i dd v dd ) + (i logic v logic ). 9 all dynamic characteristics use v dd / v ss = 2.5 v , and v logic = 2. 5 v. 10 endurance is qualified to 100,000 cycles per jedec standard 22, method a117 and measured at ?40c to +125c . 11 retention lifetime equivalent at junction temperature (t j ) = 125c per jedec standard 22, method a117. retention lifetime , based on an activation ener gy of 1 ev , derates with junction temperature in the flash/ee mem ory. www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ad5124/AD5144/AD5144a rev. 0 | page 7 of 36 electrical character istics AD5144 and AD5144a v dd = 2.3 v to 5.5 v, v ss = 0 v; v dd = 2.25 v to 2.75 v, v ss = ?2. 25 v to ?2.75 v; v logic = 1.8 v to 5.5 v, ?40c < t a < +125c, unless otherwise noted. table 3 . parameter sy mbol test conditions/comments min typ 1 max unit dc characteristics rheostat mode (all rdacs) resolution n 8 bits resistor integral nonlinearity 2 r - inl r ab = 10 k ? v dd 2.7 v ? 2 0.2 +2 lsb v dd < 2.7 v ? 5 1.5 +5 lsb r ab = 100 k ? v dd 2.7 v ? 1 0.1 +1 lsb v dd < 2.7 v ? 2 0.5 +2 lsb resistor differential nonlinearity 2 r - dnl ? 0.5 0.2 +0.5 lsb nominal resistor tolerance r ab /r ab ? 8 1 +8 % resistance temperature coefficient 3 (r ab /r ab )/t 10 6 code = full scale 35 ppm/c wiper resistance 3 r w code = zero scale r ab = 10 k ? 55 125 ? r ab = 100 k ? 130 400 ? bottom s cale or top scale r bs or r ts r ab = 10 k ? 40 80 ? r ab = 100 k ? 60 230 ? nominal resistance match r ab1 /r ab2 code = 0xff ? 1 0.2 +1 % dc characteristics potentiometer divider mode (all rdacs) integral nonlinearity 4 inl r ab = 10 k ? ? 1 0.2 +1 lsb r ab = 100 k ? ? 0.5 0.1 +0.5 lsb differential nonlinearity 4 dnl ? 0.5 0.2 +0.5 lsb full - scale error v wfse r ab = 10 k ? ? 2.5 ? 0.1 lsb r ab = 100 k ? ? 1 0.2 +1 lsb zero - scale error v wzse r ab = 10 k ? 1.2 3 lsb r ab = 100 k ? 0.5 1 lsb voltage divider temperature coefficient 3 (v w /v w )/t 10 6 code = half scale 5 ppm/c www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 8 of 36 parameter sy mbol test conditions/comments min typ 1 max unit resistor terminals maximum continuous current i a , i b , and i w r ab = 10 k ? ? 6 +6 ma r ab = 100 k ? ? 1.5 +1.5 ma terminal voltage range 5 v ss v dd v capacitance a, capacitance b 3 c a , c b f = 1 mhz, measured to gnd , code = half scale r ab = 10 k ? 25 pf r ab = 100 k ? 12 pf capacitance w 3 c w f = 1 mhz, measured to gnd, code = half scale r ab = 10 k ? 12 pf r ab = 100 k ? 5 pf common - mode leakage current 3 v a = v w = v b ? 500 15 + 500 na d igital inputs input logic 3 high v inh v logic = 1.8 v to 2.3 v 0.8 v logic v v logic = 2.3 v to 5.5 v 0.7 v logic v low v inl 0.2 v logic v input hysteresis 3 v hyst 0.1 v logic v input current 3 i in 1 a input capacitance 3 c in 5 pf digital outputs output high voltage 3 v oh r pull - up = 2.2 k ? to v logic v logic v output low voltage 3 v ol i sink = 3 ma 0.4 v i sink = 6 ma , v logic > 2.3 v 0.6 v three - state leakage current ? 1 +1 a three - state output capacitance 2 pf power supplies single - supply power range v ss = gnd 2.3 5.5 v dual - supply power range 2.25 2.75 v logic supply range single s upply, v ss = gnd 1.8 v dd v dual s upply, v ss < gnd 2.25 v dd v positive sup ply current i dd v ih = v logic or v il = gnd v dd = 5.5 v 0.7 5.5 a v dd = 2.3 v 400 na negative supply current i ss v ih = v logic or v il = gnd ? 5.5 ? 0.7 a ee prom store current 3 , 6 i dd_ee prom _store v ih = v logic or v il = gnd 2 ma ee prom read current 3 , 7 i dd_ee prom _read v ih = v logic or v il = gnd 320 a logic supply current i logic v ih = v logic or v il = gnd 1 120 na power dissipation 8 p diss v ih = v logic or v il = gnd 3.5 w power supply rejection ratio psr r ? v dd / ? v ss = v dd 10%, code = full scale ? 66 ? 60 db www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ad5124/AD5144/AD5144a rev. 0 | page 9 of 36 parameter sy mbol test conditions/comments min typ 1 max unit dynamic characteristics 9 bandw idth bw ? 3 db r ab = 10 k ? 3 mhz r ab = 100 k ? 0.43 mhz total harmonic distortion thd v dd /v ss = 2.5 v, v a = 1 v rms, v b = 0 v, f = 1 khz r ab = 10 k ? ? 80 db r ab = 100 k ? ? 90 db resistor noise density e n_wb code = half scale, t a = 25c, f = 10 khz r ab = 10 k ? 7 nv/hz r ab = 100 k ? 20 nv/hz v w settling time t s v a = 5 v, v b = 0 v, from zero scale to full scale, 0.5 lsb error band r ab = 10 k ? 2 s r ab = 100 k ? 12 s crosstalk (c w1 /c w2 ) c t r ab = 10 k ? 10 nv - sec r ab = 100 k ? 25 nv - sec analog crosstalk c ta ? 90 db endurance 10 t a = 25c 1 mcycles 100 kcycles data retention 11 50 years 1 typical values represent average readings at 25c, v dd = 5 v, v ss = 0 v, and v logic = 5 v. 2 resistor integral nonlinearity error (r - inl) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r - dnl measures the relative step change from ideal between successive tap positions. the maximum wiper current is limited to (0.7 v dd )/r ab . 3 guaranteed by design and characterization, not subject to production test. 4 inl and dnl are measured at v wb with the rdac configured as a potentiometer divider similar to a voltage output dac. v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 5 r esistor t erminal a, r e sistor t erminal b, and r esistor t erminal w have no limitations on polarity with respect to each other. dual - supply operation enables ground referenced bipolar signal adjustment . 6 different from operating current; supply current for eeprom program lasts ap proximately 30 ms. 7 different from operating current; supply current for eeprom read lasts approximately 20 s . 8 p diss is calculated from (i dd v dd ) + (i logic v logic ). 9 all dynamic characteristics use v dd / v ss = 2.5 v , and v logic = 2. 5 v. 10 endurance is qualified to 100,000 cycle s per jedec standard 22, method a117 and measured at ?40c to +125c . 11 retention lifetime equivalent at junction temperature (t j ) = 125c per jedec standard 22, method a117. retention lifetime , based on an activation ener gy of 1 ev , derates with junction temperature in the flash/ee memory. www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 10 of 36 interface timing spe cifications v logic = 1.8 v to 5.5 v; all specifications t min to t max , unless otherwise noted. table 4 . spi interface parameter 1 test conditions/comments min typ max unit description t 1 v logic > 1.8 v 20 ns sclk cycle time v logic = 1.8 v 30 ns t 2 v logic > 1.8 v 10 ns sclk high time v logic = 1.8 v 15 ns t 3 v logic > 1.8 v 10 ns sclk low time v logic = 1.8 v 15 ns t 4 10 ns sync -to - sclk falling edge setup time t 5 5 ns data setup time t 6 5 ns data hold time t 7 10 ns s ync rising edge to next sclk fall ignored t 8 2 20 ns minimum sync high time t 9 3 50 ns sclk rising edge to sdo valid t 10 500 ns sync rising edge to sdo pin disable 1 all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 2 refer to t eeprom_program and t eeprom_readback for memory commands operations (see table 6 ) . 3 r pull_up = 2.2 k ? to v dd with a capacitance load of 168 pf. table 5 . i 2 c interface parameter 1 test conditions/comments min typ max unit description f scl 2 standard mode 100 khz serial clock frequency fast mode 400 khz t 1 standard mode 4.0 s scl high time , t high fast mode 0.6 s t 2 standa rd mode 4.7 s scl low time , t low fast mode 1.3 s t 3 standard mode 250 ns d ata setup time , t su; dat fast mode 100 ns t 4 standard mode 0 3.45 s d ata hold time , t hd; dat fast mode 0 0.9 s t 5 standard mode 4.7 s s etup time for a repeated start condition , t su; sta fast mode 0.6 s t 6 standard mode 4 s h old time (repeated) for a start condition , t hd; sta fast mode 0.6 s t 7 standard mode 4.7 s b us free time between a stop and a st art condition , t buf fast mode 1.3 s t 8 standard mode 4 s s etup time for a stop condition , t su; sto fast mode 0.6 s t 9 standard mode 1000 ns r ise time of sda signal , t rda fast mode 20 + 0.1 c l 300 ns t 10 standard mode 300 ns f all time of sda signal , t fda fast mode 20 + 0.1 c l 300 ns t 11 standard mode 1000 ns r ise time of scl signal , t rcl fast mode 20 + 0.1 c l 300 ns t 11a standard mode 1000 ns r ise time of scl signal after a repeated start condition and after an acknowledge bit , t rcl1 (not shown in figure 5 ) fast mode 20 + 0.1 c l 300 ns www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ad5124/AD5144/AD5144a rev. 0 | page 11 of 36 parameter 1 test conditions/comments min typ max unit description t 12 standard mode 300 ns f all time of scl signal , t fcl fast mode 20 + 0.1 c l 300 ns t sp 3 fast mod e 0 50 ns pulse width of suppressed spike 1 maximum bus capacitance is limited to 400 pf. 2 the sda and scl timing is measured with the input filters enabled. switching off the input filters improves the transfer rate ; however, it has a negative effect on the emc behavior of the part. 3 input filtering on the scl and sda inputs suppresses noise spikes that are less than 50 ns for fast mode. table 6 . control pins parameter min typ max unit description t 1 1 s end command to lrdac falling edge t 2 50 ns minimum lrdac l ow time t 3 0.1 10 s reset low time t eeprom_program 1 15 50 ms memory program time (not shown in figure 8 ) t eeprom_readback 7 30 s memory readback time (not shown in figure 8 ) t power_up 2 75 s start - up time (not shown in figure 8 ) t reset 30 s reset eeprom restore time (not shown in figure 8 ) 1 ee prom program time depends on the temperature and eeprom write cycles. higher timing is expected at lower temp erature s and higher write cycles. 2 maximum time after v dd ? v ss is equal to 2.3 v. shi f t r egister and timing d iagrams data bits db8 db15 (msb) db0 (lsb) d7 d6 d5 d4 d3 d2 d1 d0 address bits a0 a1 a2 c2 c1 c0 a3 c3 control bits 10877-004 db7 figure 4 . input shift register content s t 7 t 6 t 2 t 4 t 11 t 12 t 6 t 5 t 10 t 1 scl sda p s s p t 3 t 8 t 9 10877-005 figure 5. i 2 c serial interface timing diagram (typical write sequence) www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 12 of 36 c3 t 4 t 2 t 3 t 5 t 6 c2 c1 c0 d7 d6 d5 d2 d1 d0 sdi *previous command received. sclk sync c3* sdo c2* c1* c0* d7* d6* d5* d2* d1* d0* t 8 t 9 t 10 t 7 t 1 10877-006 figure 6 . spi serial interface timing diagram, cpol = 0, cpha = 1 c3 t 4 t 2 t 3 t 5 t 6 c2 c1 c0 d7 d6 d5 d2 d1 d0 sdi *previous command received. sclk sync c3* sdo c2* c1* c0* d7* d6* d5* d2* d1* d0* t 8 t 9 t 10 t 7 t 1 10877-007 figure 7 . spi serial interface timing diagram, cpol = 1, cpha = 0 spi interface i 2 c interface scl sclk sync sda lrdac reset p t 1 t 2 t 3 10877-008 figure 8 . control pins timing diagram www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ad5124/AD5144/AD5144a rev. 0 | page 13 of 36 absolute maximum rat ings t a = 25c, unless otherwise noted. table 7 . parameter rating v dd to gnd ? 0.3 v to +7.0 v v ss to gnd + 0.3 v to ? 7.0 v v dd to v ss 7 v v logic to gnd ? 0.3 v to v dd + 0.3 v or +7.0 v (whichever is less) v a , v w , v b to gnd v ss ? 0.3 v, v dd + 0.3 v i a , i w , i b pulsed 1 frequency > 10 khz r aw = 10 k? 6 ma/d 2 r aw = 100 k? 1.5 ma/d 2 frequency 10 khz r aw = 10 k? 6 ma/d 2 r aw = 100 k? 1.5 ma/d 2 digital inputs ? 0.3 v to v lo gic + 0.3 v or +7 v (whichever is less) operating temperature range, t a 3 ? 40 c to +125c maximum junction temperature, t j m ax imum 150c storage temperature range ? 65c to +150c reflow soldering peak temperature 260c time at peak temperature 20 s ec to 40 sec package power dissipation (t j max ? t a )/ ja esd 4 4 kv ficdm 1.5 kv 1 maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 d = p ulse duty factor . 3 includes programming of eeprom memory. 4 human body model (hbm) classification . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at th ese or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is defined by the j edec jesd51 standard, and the value is dependent on the test board and test environment. table 8 . thermal resistance package type ja jc unit 24- lead lfcsp 35 1 3 c/w 20- lead tssop 143 1 45 c/w 1 jedec 2s2p test board, still air (0 m/s ec airflow). esd caution www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 14 of 36 pin configuration s and function descrip tions 1 2 3 4 5 6 7 8 9 10 gnd a1 w1 w3 a3 b1 sync a2 v ss b3 20 19 18 17 16 15 14 13 12 1 1 sdi sclk v logic w4 b4 v dd w2 b2 a4 sdo ad5124/ AD5144 top view (not to scale) 10877-010 figure 9 . 20 - lead tssop, spi interface pin configuration ( ad5124/ AD5144 ) table 9 . 20 - lead tssop, spi interface pin function descriptions ( ad5124 / AD5144 ) pin no. mnemonic descriptio n 1 sync synchronization data input , active low. when sync returns high, data is loaded into the input shift register. 2 gnd ground pin, logic ground reference. 3 a1 terminal a of rdac1. v ss v a v dd . 4 w1 wiper te rminal of rdac1. v ss v w v dd . 5 b1 terminal b of rdac1. v ss v b v dd . 6 a3 terminal a of rdac3. v ss v a v dd . 7 w3 wiper terminal of rdac3. v ss v w v dd . 8 b3 terminal b of rdac3. v ss v b v dd . 9 v ss negative power supply. decouple this pin with 0.1 f ceramic capacitors and 10 f capacitors. 10 a2 terminal a of rdac2. v ss v a v dd . 11 w2 wiper terminal of rdac2. v ss v w v dd . 12 b2 terminal b of rdac2. v ss v b v dd . 13 a4 terminal a of rdac4. v ss v a v dd . 14 w4 wiper terminal of rdac4. v ss v w v dd . 15 b4 terminal b of rdac4. v ss v b v dd . 16 v dd positive power supply. decouple this pin with 0.1 f ceramic capacitors and 10 f capacitors. 17 v logic logic power supply; 1.8 v to v dd . decouple this pin with 0.1 f ceramic c apacitors and 10 f capacitors. 18 sclk serial clock line. data is clocked in at the logic low transition. 19 sdi serial data input . 20 sdo serial data output. this is an o pen - drain output pin, and it needs an external pull - up resistor. www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ad5124/AD5144/AD5144a rev. 0 | page 15 of 36 1 2 3 4 5 6 7 8 9 10 gnd a1 w1 w3 a3 b1 reset a2 v ss b3 20 19 18 17 16 15 14 13 12 1 1 sd a sc l v logic w4 b4 v dd w2 b2 a4 addr AD5144a top view (not to scale) 10877-0 1 1 figure 10 . 20 - lead tssop , i 2 c interface pin configuration ( AD5144a ) table 10 . 20- lead tssop , i 2 c interface pin function descriptions ( AD5144a ) pin no. mnemonic description 1 reset hardware reset pin. refresh the rdac registers from eeprom . reset is activated at the logic low. if this pin is not used, t ie reset to v logic . 2 gnd ground pin, logic ground reference. 3 a1 terminal a of rdac1. v ss v a v dd . 4 w1 wiper t erminal of rdac1. v ss v w v dd . 5 b1 terminal b of rdac1. v ss v b v dd . 6 a3 terminal a of rdac3. v ss v a v dd . 7 w3 wiper t erminal of rdac3. v ss v w v dd . 8 b3 terminal b of rdac3. v ss v b v dd . 9 v ss negative powe r supply. decouple this pin with 0.1 f ceramic capacitors and 10 f capacitors. 10 a2 terminal a of rdac2. v ss v a v dd . 11 w2 wiper t erminal of rdac2. v ss v w v dd . 12 b2 terminal b of rdac2. v ss v b v dd . 13 a4 terminal a of rdac4. v ss v a v dd . 14 w4 wiper t erminal of rdac4. v ss v w v dd . 15 b4 terminal b of rdac4. v ss v b v dd . 16 v dd positive power supply. decouple this pin with 0.1 f ceramic capacitors and 10 f capacitors. 17 v logic logic power supply; 1.8 v to v dd . decouple th is pin with 0.1 f ceramic capacitors and 10 f capacitors. 18 scl serial clock line. data is clocked in at the logic low transition. 19 sda serial data input/output . 20 addr programmable a ddress for multiple package decoding. www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 16 of 36 10877-009 pin 1 indic a t or 1 gnd 2 a1 3 w1 4 b1 5 a3 6 w3 15 v dd 16 v logic 17 scl/sclk notes 1. internally connect the exposed pad to v ss . 18 dis 14 b4 13 w4 7 b3 8 v ss 9 a2 1 1 b2 12 a4 10 w2 21 addr1/sdo 22 addr0/sync 23 lrdac 24 reset 20 w p 19 sda/sdi ad5124/ AD5144 t o p view (not to scale) figure 11 . 24 - lead lfcsp pin configuration ( ad5124 / AD5144 ) table 11 . 24- lead lfcsp pin function descriptions ( ad5124 / AD5144 ) pin no. mnemonic description 1 gnd ground pin, logic ground reference. 2 a1 terminal a of rdac1. v ss v a v dd . 3 w1 wiper terminal of rdac1. v ss v w v dd . 4 b 1 terminal b of rdac1. v ss v b v dd . 5 a3 terminal a of rdac3. v ss v a v dd . 6 w3 wiper terminal of rdac3. v ss v w v dd . 7 b3 terminal b of rdac3. v ss v b v dd . 8 v ss negative power supply. decouple this pin with 0.1 f ceramic capacitors and 1 0 f capacitors. 9 a2 terminal a of rdac2. v ss v a v dd . 10 w2 wiper terminal of rdac2. v ss v w v dd . 11 b2 terminal b of rdac2. v ss v b v dd . 12 a4 terminal a of rdac4. v ss v a v dd . 13 w4 wiper terminal of rdac4. v ss v w v dd . 14 b4 termi nal b of rdac4. v ss v b v dd . 15 v dd positive power supply. decouple this pin with 0.1 f ceramic capacitors and 10 f capacitors. 16 v logic logic power supply; 1.8 v to v dd . decouple this pin with 0.1 f ceramic capacitors and 10 f capacitors. 17 sc l/sclk i 2 c serial clock line (scl) . data is clocked in at the logic low transition. spi serial clock line (sclk). data is clocked in at the logic low transition. 18 dis digital interface select (spi/i 2 c select). spi when dis = 0 (gnd), and i 2 c when di s = 1 (v logic ). this pin cannot be left floating. 19 sda/sdi serial data input/output (sda), when dis = 1. serial data input (sdi), when dis = 0. 20 wp optional write protect. this pin prevents any changes to the present rdac and eep rom content, except when reload ing the content of the eeprom into the rdac register. wp is activated at logic low. if this pin is not used, tie wp to v logic . 21 addr1/sdo programmable address (addr1) for multiple packag e decoding, when dis = 1. serial data output (sdo). open - drain output, needs an external pull - up resistor, when dis = 0. 22 addr0/ sync programmable address (addr0) for multiple package decoding, when dis = 1. synchronization data input , when dis = 0 . this pin is active low. when sync returns high, data is loaded into the input shift register . 23 lrdac load rdac. transfers the contents of the input registers to their respective rdac registers whe n their associated input registers were previously loaded using command 2 ( see table 20) . this allows simultaneous update of all rdac registers . lrdac is activated at the high - to - low transition. if not used, tie lrdac to v logic . 24 reset hardware reset pin. refresh the rdac registers from eeprom . reset is activated at the logic low. if not used, tie reset to v logic . epad internally connec t t he exposed pad to v ss . www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ad5124/AD5144/AD5144a rev. 0 | page 17 of 36 typical performance characteristics ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 100 200 r-inl (lsb) code (decimal) 10k ?, +125c 10k ?, +25c 10k ?, ?40c 100k ?, +125c 100k ?, +25c 100k ?, ?40c 10877-012 figure 12 . r - inl vs. code ( AD5144 /AD5144a ) r-inl (lsb) code (decimal) ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0 50 100 10k ?, +125c 10k ?, +25c 10k ?, ?40c 100k ?, +125c 100k ?, +25c 100k ?, ?40c 10877-013 figure 13 . r - inl vs. code ( ad5124 ) 0 100 200 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 in l (lsb) code (decimal) 10k ?, ?4 0 c 10k ?, + 25 c 10k ?, + 12 5 c 100k ?, ?4 0 c 100k ?, + 25 c 100k ?, + 12 5 c 10877-014 figure 14 . inl vs. code ( AD5144 / AD5144a ) ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0 100 200 r-dn l (lsb) 10877-015 code (decimal) 10k ?, +125c 10k ?, +25c 10k ?, ?40c 100k ?, +125c 100k ?, +25c 100k ?, ?40c figure 15 . r - dnl vs. code ( AD5144 /AD5144a ) code (decimal) ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0 50 100 r-dn l (lsb) 10877-016 10k ?, +125c 10k ?, +25c 10k ?, ?40c 100k ?, +125c 100k ?, +25c 100k ?, ?40c figure 16 . r - dnl vs. code ( ad5124 ) ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 dn l (lsb) code (decimal) 10k ?, ?4 0 c 10k ?, +2 5 c 10k ?, +12 5 c 100k ?, ?4 0 c 100k ?, +2 5 c 100k ?, +12 5 c 10877-017 0 100 200 figure 17 . dnl vs. code ( AD5144 / AD5144a ) www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 18 of 36 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0 50 100 in l (lsb) code (decimal) 10877-018 10k ?, ?4 0 c 10k ?, + 2 5 c 10k ?, + 12 5 c 100k ?, ?4 0 c 100k ?, + 2 5 c 100k ?, + 12 5 c figure 18 . inl vs. code ( ad5124 ) 10877-019 ?50 0 50 100 150 200 250 300 350 400 450 potentiometer mode temperature coefficient (ppm/c) code (decimal) 100k ? 10k ? 0 5 0 10 0 15 0 20 0 25 5 0 2 5 5 0 7 5 10 0 12 7 ad 512 4 ad 514 4/ AD5144a figure 19 . potentiometer mode temp erature c o efficient (( v w /v w )/ t 10 6 ) vs. code 0 100 200 300 400 500 600 700 800 ?40 10 60 125 1 10 current (na) temper a ture (c) 10877-020 i dd , v dd = 2.3v i dd , v dd = 3.3v i dd , v dd = 5v i logic , v logic = 2.3v i logic , v logic = 3.3v i logic , v logic = 5v v dd = v logic v ss = gnd figure 20 . supply current vs. temp erature ?0.14 ?0.12 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0 50 100 dn l (lsb) code (decimal) 10877-021 10k ?, ?4 0 c 10k ?, +2 5 c 10k ?, +12 5 c 100k ?, ?4 0 c 100k ?, +2 5 c 100k ?, +12 5 c figure 21 . dnl vs. code ( ad5124 ) ad 512 4 ad 514 4/ AD5144a ?50 0 50 100 150 200 250 300 350 400 450 rh e o s t a t m o d e t empe ra t ur e c o e ff i c i e n t ( pp m / c ) 10k? 100k? 10877-122 code (decimal) 0 5 0 10 0 15 0 20 0 25 5 0 2 5 5 0 7 5 10 0 12 7 figure 22 . rheosta t mode temperature coefficient (( r wb /r wb )/ t 10 6 ) vs. code 0 200 400 600 800 1000 1200 0 1 2 3 4 5 i logic current ( a) input volatge (v) 10877-023 i 2 c, v logic = 1.8v i 2 c, v logic = 2.3v i 2 c, v logic = 3.3v i 2 c, v logic = 5v i 2 c, v logic = 5.5v spi, v logic = 1.8v spi, v logic = 2.3v spi, v logic = 3.3v spi, v logic = 5v spi, v logic = 5.5v figure 23 . i logic current vs. digital input voltage www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ad5124/AD5144/AD5144a rev. 0 | page 19 of 36 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m gain (db) frequenc y (hz) AD5144/AD5144a (ad5124) 10877-022 0x80 (0x40) 0x40 (0x20) 0x20 (0x10) 0x10 (0x08) 0x8 (0x04) 0x4 (0x02) 0x2 (0x01) 0x1 (0x00) 0x00 figure 24 . 10 k? gain vs. frequency vs. code ?100 ?90 ?80 ?70 ?60 ?50 ?40 20 200 2k 20k 200k thd + n (db) frequenc y (hz) 10k ? 100k ? 10877-025 v dd /v ss = 2.5v v a = 1v rms v b = gnd code = half scale noise filter = 22khz figure 25 . total harmonic distortion plus noise (thd + n) vs. frequency ?100 ?80 ?60 ?40 ?20 0 20 10 100 1k 10k 100k 1m 10m phase (degrees) frequenc y (hz) 10877-026 quarter scale midscale full-scale v dd /v ss = 2.5v r ab = 10k figure 26 . normalized phase flatness vs. frequency, r ab = 10 k? ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 gain (db) frequenc y (hz) 10 100 1k 10k 100k 1m 10m 10877-123 0x80 (0x40) 0x40 (0x20) 0x20 (0x10) 0x10 (0x08) 0x8 (0x04) 0x4 (0x02) 0x2 (0x01) 0x1 (0x00) 0x00 AD5144/AD5144a (ad5124) figure 27 . 100 k? gain vs. frequency vs. code 10k ? 100k ? ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0.001 0.01 0.1 1 thd + n (db) vo lt age (v rms) v dd /v ss = 2.5v f in = 1khz code = half scale noise filter = 22 khz 10877-028 figure 28 . total harmonic distortion plus noise (thd + n) vs. amplitude ?80 ?90 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 10 100 1k 10k 100k 1m phase (degrees) frequenc y (hz) quarter scale midscale full-scale 10877-029 v dd /v ss = 2.5v r ab = 100k figure 29 . normalized phase flatness vs. frequency, r ab = 100 k? www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 20 of 36 0 100 200 300 400 500 600 0 1 2 3 4 5 wiper on resis t ance ( ) volt age (v) 100k, v dd = 2.3v 100k, v dd = 2.7v 100k, v dd = 3v 100k, v dd = 3.6v 100k, v dd = 5v 100k, v dd = 5.5v 10k, v dd = 2.3v 10k, v dd = 2.7v 10k, v dd = 3v 10k, v dd = 3.6v 10k, v dd = 5v 10k, v dd = 5.5v 10877-030 figure 30 . incremental wiper on resistance vs. positive power supply (v dd ) 10877-031 0 1 2 3 4 5 6 7 8 9 10 0 20 40 60 80 100 120 0 10 20 30 40 50 60 bandwidth (mhz) code (decimal) AD5144/ AD5144a ad5124 10k ? + 0pf 10k ? + 75pf 10k ? + 150pf 10k ? + 250pf 100k ? + 0pf 100k ? + 75pf 100k ? + 150pf 100k ? + 250pf figure 31 . maximum bandwidth vs. code vs. net capacitance ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 5 10 15 rel a tive vo lt age (v) time ( s) 0x80 to 0x7f, 100k 0x80 to 0x7f, 10k 10877-032 v dd /v ss = 2.5v v a = v dd v b = v ss figure 32 . maximum transition glitch 0 0 . 2 0 . 4 0 . 6 0 . 8 1 . 0 1 . 2 0 0 . 0 00 5 0 . 0 01 0 0 . 0 01 5 0 . 0 02 0 0 . 0 02 5 ?40 0 ?50 0 ?60 0 ?30 0 ?20 0 ?10 0 0 10 0 20 0 3 0 0 40 0 50 0 60 0 cu m u l a ti ve pr o bab ili t y p r o bab ili t y d e n s it y r es i s t o r dr i ft ( pp m ) 10877-033 figure 33 . resistor life t ime drift ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 100 1k 10k 100k 1m 10m psrr (db) frequenc y (hz) 10k 100k 10877-034 v dd = 5v 10% ac v ss = gnd, v a = 4v, v b = gnd code = midscale figure 34 . power supply rejection ratio (psrr) vs. frequency ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 0.020 0 500 1000 1500 2000 rel a tive vo lt age (v) time (ns) 10877-035 v dd /v ss = 2.5v v a = v dd v b = v ss code = half scale figure 35 . digital feedthrough www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ad5124/AD5144/AD5144a rev. 0 | page 21 of 36 ?120 ?100 ?80 ?60 ?40 ?20 0 10 100 1k 10k 100k 1m 10m gain (db) frequenc y (hz) 10k 100k 10877-036 shutdown mode enabled figure 36 . shutdown isolation vs. frequency 0 1 2 3 4 5 6 7 0 50 100 150 200 250 0 25 50 75 100 125 ad5124 theoretica l i max (ma) AD5144/ AD5144a 100k? 10k? code (decimal) 10877-037 figure 37 . theoretical maximum current vs. code www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 22 of 36 test circuits figure 38 to figure 42 define the test conditions used in the specifications section. a w b nc i w dut v ms nc = no connect 10877-038 figure 38 . resistor integral nonlinearity error (rheostat operation; r - inl, r - dnl) a w b dut v ms v+ v+ = v dd 1lsb = v+/2 n 10877-039 figure 39 . potentiometer divider nonlinearity error (inl, dnl) a w nc b dut i w = v dd /r nomina l v ms1 v w r w = v ms1 /i w 10877-040 nc = no connect figure 40 . wiper resistance a w b v ms v+ = v dd 10% psrr (db) = 20 log v ms v dd ( ) ~ v a v dd v ms % v dd % pss ( %/% ) = v+ 10877-041 figure 41 . power supply sensitivity and power supply rejection ratio (pss and psrr) + ? dut code = 0x00 0.1v v ss t o v dd r sw = 0.1v i sw i sw w b a = nc 10877-045 figure 42 . incremental on resistance www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ad5124/AD5144/AD5144a rev. 0 | page 23 of 36 theory of operation the ad5124 / AD5144 / AD5144a digital programmable potentiometers are designed to operate as true variable resistors for analog signals within the terminal voltage range of v ss < v term < v dd . the resistor wiper position is determined by the rdac register contents. the rdac register acts as a scratchpad register that allows unlimited changes of resistance settings. a secondary register (the input register ) can be used to preload the rdac register data. the rdac register can be programmed with any position setting using the i 2 c or spi interface (depending on the model). when a desirable wiper position is found, this value can be stored in the eeprom memory. thereafter, the wiper position is always restored to that position for subsequent power - up s . the storing of the eeprom data takes approximately 1 5 ms; during this time, the device is locked and does not acknowledge any new command , preventing any changes from taking place. rdac r egister a nd eeprom the rdac register directly controls the position of the digital potentiometer wiper. for example, when the rdac register is loaded with 0x80 ( AD5144 / ad514 4a , 256 taps), the wiper is connected to half scale of the variable resistor. the rdac register is a standard logic register; there is no restriction on the number of changes allowed . it is possible to both write to and read from the rdac register using the digital interface ( see table 14) . the contents of the rdac register can be stored to the eeprom using c ommand 9 ( see table 14) . thereafter , the rdac register always set s at that position for any future on - off - on power supply sequence. it is possible to read back data saved into the eeprom with c ommand 3 ( see table 14) . alternatively, the eeprom can be writ t e n to independently usi ng c ommand 1 1 ( see table 20) . input shift register for the ad5124 / AD5144 / ad5 144a , the input shift register is 16 bits wide, as shown in figure 4 . the 16 - bit word consists of four control bits, followed by four address bits and by eight data bits . i f the ad5124 rdac or ee prom registers are read from or written to , the lowe st data bit (bit 0) is ignored. data is loaded msb first (bit 15). the four control bits determine the function of the software command , as listed in table 14 and table 20. serial data d igital interface s election , dis the ad5124 / AD5144 lfscp provides the flexibility of a selectabl e interface. when the digital interface select (dis) pin is tied low, the spi mode is engaged. when the dis pin is tied high, the i 2 c mode is engaged. spi serial data inte rface the ad5124 / AD5144 contain a 4 - wire , spi - compatible digital interface (sdi, sync , sdo , and sclk). the write sequence begins by bringing the sync line low. the sync pin must be held low unti l the complete data - word is loaded from the sdi pin. data is loaded in at the sclk falling edge transition, as shown in figure 6 . when sync returns high, the serial data - word is decoded according to the instructions in table 20. to minimize power consumption in the digital input buffers when the part is enable d , operate all serial interface pins close to the v logic supply rails. sync interruption in a sta ndalone write sequence for the ad5124 / AD5144 , the sync line is kept low for 16 falling edges of sclk, and the instruction is decoded when sync is pulled high. however, if the sync line is kept low for less than 16 falling edges of sclk, the input shift register content is ignored , and the write sequence is considered invalid. sdo p in the serial data output pin (sd o) serves two purposes : to read back the contents of the control , ee prom , rdac , and input registers using command 3 (see table 14 and table 20 ), and to connect the ad5124 / AD5144 in daisy - chain mode. the sdo pin contains an internal open - drain output that needs an external pull - up resistor. th e sdo pin is enabled when sy nc is pulled low , and t he data is clocked out of sdo on the rising edge of sclk, as shown in figure 6 and figure 7 . www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 24 of 36 daisy - chain connection d aisy chaining min imizes the number of port pins required from the controlling ic. as shown in figure 43, the sdo pin of one package must be tie d to the sdi pin of the next package. the clock period may need to be increase d because of the propagation delay of the line between subsequent devices. when two ad5124 / AD5144 devices are daisy chained, 32 bits of data are required. the first 16 bits are assigned to u2, and the second 16 bits are assigned to u1, as shown in figure 44 . keep the sync pin low until all 32 bits are clocked into their respective serial registers. the sync pin is then pulled high to complete the operation. to prevent data from mislocking ( for example, due to noise) the part includes an internal counter, if the sclk falling edges count is not a multiple of 8, the part ignores the command . a valid clock count is 16, 24, 32 , 40 , and so on. the counter resets when sync returns high. mosi ss sclk miso microcontroller sdi sdo sclk sclk r p 2.2k? r p 2.2k? sdi sdo u1 u2 ad5124/ AD5144 ad5124/ AD5144 sync v logic sync dais y -chain v logic 10877-046 figure 43 . daisy - chain configuration db15 sclk sync mosi 1 2 16 db0 db15 sdo_u1 32 db15 db0 db15 db0 17 18 db0 input word for u2 input word for u1 input word for u2 undefined 10877-047 figure 44 . daisy - chain diagram www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ad5124/AD5144/AD5144a rev. 0 | page 25 of 36 i 2 c serial d ata interface the AD5144 / AD5144a have 2 - wire , i 2 c - compatible serial interfaces. these devices can be connected to an i 2 c bus as a slave device, under the control o f a master device . see figure 5 for a timing diagram of a typical write sequence. the AD5144 / AD5144a support standard (100 khz) and fast (400 khz) data transfer modes. support is not provided for 10- bit addressing and general call addressing. the 2 - wire serial bus protocol operates as follows: 1. the master initiates a data transfer by establishing a start condition, which is when a high - to - l ow transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7 - bit slave address and a n r/ w bit. the slave device corresponding to the transmitted address responds by pulling sda lo w during the ninth clock pulse (this is call ed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. if the r/ w bit is se t high, the master reads from the slave device. however, if the r/ w bit is set low, the master writes to the slave device. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowled ge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits have been read from or written to , a stop condition is established. in write mode, the master pulls the sda line high during the ten th clock pulse to establish a stop condition. in read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master then brings the sda line low before the ten th clock p ulse, an d then high again during the ten th clock pulse to establish a stop condition. i 2 c address the AD5144 / AD5144a each have two different device address options availab le (see table 12 and table 13). table 12 . 20- lead tssop device address selection addr 7 - bit i 2 c device address v dd 0101000 no connect 1 0101010 gnd 0101011 1 n ot available in bipolar mode ( v ss < 0 v ) or in low voltage mode ( v logic = 1.8 v ) . table 13 . 24- lead lfcsp device address selection addr0 pin addr1 pin 7 - bit i 2 c device address v dd v dd 0100000 no connect 1 v dd 010001 0 gnd v dd 0100011 v dd no connect 1 0101000 no connect 1 no connect 1 0101010 gnd no connect 1 0101011 v dd gnd 0101100 no connect 1 gnd 0101110 gnd gnd 0101111 1 not available in bipolar mode ( v ss < 0 v ) or in low voltage mode ( v logic = 1.8 v ) . www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 26 of 36 table 14. reduced commands operation truth table command number control bits [db15:db12] address bits [db11:db8] 1 data bits [db7:db0] 1 c3 c2 c1 c0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 0 x x x x x x x x x x x x nop: do nothing. 1 0 0 0 1 0 0 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data to rdac 2 0 0 1 0 0 0 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data to input register 3 0 0 1 1 x 0 a1 a0 x x x x x x d1 d0 read back contents d1 d0 d ata 0 1 eeprom 1 1 rdac 9 0 1 1 1 0 0 a1 a0 x x x x x x x 1 copy rdac register to eeprom 10 0 1 1 1 0 0 a1 a0 x x x x x x x 0 copy eeprom into rdac 14 1 0 1 1 x x x x x x x x x x x x software reset 15 1 1 0 0 a3 0 a1 a0 x x x x x x x d0 software shutdown d0 condition 0 normal mode 1 shutdown mode 1 x = dont care. table 15. reduced addres s bits table a3 a2 a1 a0 channel stored channel memory 1 0 x 1 x 1 all channels not applicable 0 0 0 0 rdac1 rdac1 0 0 0 1 rdac2 rdac2 0 0 1 0 rdac3 rdac3 0 0 1 1 rdac4 rdac4 1 x = dont care. www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ad5124/AD5144/AD5144a rev. 0 | page 27 of 36 advanced control mod es the ad5124 / AD5144 / AD5144a digital potentiometers include a set of user programming features to address the wide number of application s for these universal adjustment devices ( see table 20 and table 22) . key programming features include the following: ? input register ? linear gain setting mode ? low wiper resistance feature ? linea r i ncrement and decrement instructions ? 6 db increment and decrement instructions ? burst m ode (i 2 c only) ? reset ? shutdown mode input r egister the ad5124 / AD5144 / AD5144a include one input register per rdac register. th ese register s allow preload ing of the value for the associate d rdac register. the se register s can be written to using command 2 and read back from using command 3 (see table 20 ). this feature allows a synchronous and asynchronous update of one or all of the rdac registers at the same time. the transfer from the input register to the rdac register is done asynchronously by the lrdac pin or synchronously by c ommand 8 (see table 20) . if new data is loaded in to a n rdac register , th is rdac register automatically overwrites the associate d input register. linear gain setting mode the patented arc hitecture of the ad5124 / AD5144 / AD5144a allows the independent control of each string resistor, r aw , and r wb . to enabl e this feature , use command 16 (see table 20 ) to set b it d2 of the control register ( see table 22) . this mode of operation can control the potentiometer as two independent rheostats connected at a single point, the w terminal. this feature enable s a second input and a n rdac register per channel, as shown in table 21 , but the actual rdac content s remain unchanged . the same operations are valid for potentiometer and linear gain setting mode s. the eeprom commands affect the r wb resistance only . the part s restores in potentiometer mode after a reset or power - up. low wiper resistance f eature the ad5124 / AD5144 / AD5144a include two commands to reduce the wiper resistance between the terminals when the device s achieve full scale or zero scale. these ext ra positions are called bottom scale, bs, and top scale, ts. the resistance between t erminal a and t erminal w at top scale is specified as r ts . s imilar ly , the bottom scale re si stance between t erminal b and terminal w is specifi ed as r bs . the contents of the rdac registers are unchanged by entering in to these position s. there are t hree ways to exit f r o m top scale and bottom scale : by using c ommand 12 or command 13 (see table 20) ; by loading new data in a n rdac register, which includes increment/decrement operati ons ; or by entering shutdown mode, command 15 (see table 20) . table 16 and table 17 show the truth tables for the top scale position and the botto m scale position , respectively, when the potentiometer or linear gain setting mode is enable d . table 16. top scale truth table linear gain setting mode potentiometer m ode r aw r wb r aw r wb r ab r ab r ts r ab table 17. bottom scale truth table linear gain setting mode potentiometer m ode r aw r wb r aw r wb r ts r bs r ab r bs linear increment and decrement instructions the increment and decrement commands ( command 4 and command 5 in table 20 ) are useful for linear step adjustment applications. these commands simplify microcontroller software coding by allowing the controller to send an increment or decrement command to the device. the adjustment can be individual or in a ganged potentiometer arrangement , where all wiper positions are changed at the same time. for an increment command, executing command 4 automatically moves the wiper to the next rdac position . this command can be executed in a single channel or multiple channels . www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 28 of 36 6 db increment and decrement instructions two programming instructions produce logarithmic taper increment or decrement of the wiper position control by an individual potentiometer or by a ganged potentiometer arrangement where all rdac register positions are changed simultaneously . the +6 db increment is activated by command 6, and the ? 6 db decrement is activated by command 7 ( see table 20) . for example, starting with the zero - scale position and executing command 6 ten times moves the wiper in 6 db steps to the full - scale position . when the wiper position is ne ar the maximum setting, the last 6 db increment instruction cause s the wiper to go to the full - scale position ( see table 18) . incr ementing the wiper position by + 6 db essentially doubles the rdac register value, whereas decrementi ng the wiper position by ? 6 db halves the register value . internally, the ad5124 / AD5144 / AD5144a use shift registers to shift the bits left an d right to achieve a 6 db increment or decrement. these functions are useful for various audio/video level adjustments, especially for white led brightness settings in which human visual responses are more sensitive to large adjustments than to small adju stments. table 18 . detailed left shift and right shift functions for the 6 db step increment and decrement left shift (+6 db/step) right shift ( ? 6 db/step) 0000 0000 1111 1111 0000 0001 0111 1111 0000 0010 0011 1111 0000 0100 0001 1111 0000 1000 0000 1111 0001 0000 0000 0111 0010 0000 0000 0011 0100 0000 0000 0001 1000 0000 0000 0000 1111 1111 0000 0000 burst mode (i 2 c only) by enabli ng th e burst mode, multiple data bytes can be sent to t he part consecutively. after the command byte, the part interprets the following consecutive bytes as data bytes for the command. a new command can be sent by generating a repeat start or by a stop and start condition. th e burst mode is activ ated by setting bit d3 of the control register (see table 22). reset the ad5124 / AD5144 / AD5144a can be reset through software by executing command 14 (see table 20 ) o r through hardware on the low pulse of the reset pin. the reset command loads the rdac register w ith the contents of the eeprom and takes approximately 30 s. the eeprom is preloaded to midscale at the factory, and initial power - up is, accordingly, at midscale. tie reset to v dd if the reset pin is not used. shutdown mode the ad5124 / AD5144 / AD5144a can be placed in shutdown mode by executing the software shutdown command, command 1 5 (see table 20 ), and setting the lsb (d0) to 1. this feature places the rdac in a zero power consumption state where the device operates in potentiometer mode , terminal a is open circuited , and the wiper, terminal w , is connected to terminal b ; however, a finite wiper resistance of 40 is present. when the device is configured in linear gain setting mode , the resistor addressed, r aw or r wb , is int ernally place at high impedance . table 19 shows a truth table depending o n the device operating mode. the contents of the rdac register are unchanged by entering shutdown mode . however, all commands listed in table 20 are supported while in shutdown mode. execute command 15 (see table 20 ) and set the lsb (d0) to 0 to exit shutdown mode. table 19. shutdown mode truth table linear gain setting mode potentiometer mode r aw r wb r aw r wb high i mpedance high i mpedance high i mpedance r bs eeprom or rdac register protection the eeprom and rdac registers can be protected by disabling any update to th e se registers . this can be done by using software or by using hardware. if the se regist ers are protect ed by software, set bit d0 and/or bit d1 ( see table 22 ) , which protect s the rdac and eeprom registers independently . if the registers are protected by hardware, pull the wp pin low (only available in the lfcsp package) . if the wp pin is pulled low when the part is executing a command, the protection is not enabled until the command is completed (only available in the lfcsp package) . when rdac is protected, the only operation allowed is to copy the eeprom into the rdac register . load rdac input regi ster ( lrdac ) lrdac software or hardware transfer s data from the input register to the rdac register (and therefore updates the wiper pos ition). by default, the input register has the same value as the rdac register; therefore, only the input register that has been updated using command 2 is updated. software lrdac , command 8, allows updating of a single rdac register or a ll of the channels at once (see table 20 ). this is a synchronous update. the h ardware lrdac is completely asynchronous and cop ies the content of all the input register s into the associated rdac register s. if a co mmand is being execut ed , a ny transition in the lrdac pin is ignored by the part to avoid data corruption . www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ad5124/AD5144/AD5144a rev. 0 | page 29 of 36 table 20 . advance command s operation truth table command number co ntrol bits [db15:db12] address bits [db 11:db8] 1 data bits [db7:db0] 1 c3 c2 c1 c0 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 operation 0 0 0 0 0 x x x x x x x x x x x x nop: do nothing 1 0 0 0 1 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data to rdac 2 0 0 1 0 a3 a2 a1 a 0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data to input register 3 0 0 1 1 x a2 a1 a0 x x x x x x d1 d0 read back contents d1 d0 d ata 0 0 input register 0 1 eeprom 1 0 control register 1 1 rdac 4 0 1 0 0 a3 a2 a1 a0 x x x x x x x 1 linear rdac increment 5 0 1 0 0 a3 a2 a1 a0 x x x x x x x 0 linear rdac decrement 6 0 1 0 1 a3 a2 a1 a0 x x x x x x x 1 + 6 db rdac increment 7 0 1 0 1 a3 a2 a1 a0 x x x x x x x 0 ? 6 db rdac decrement 8 0 1 1 0 a3 a2 a1 a0 x x x x x x x x copy input register to rdac (software lrdac ) 9 0 1 1 1 0 0 a1 a0 x x x x x x x 1 copy rdac register to eeprom 10 0 1 1 1 0 0 a1 a0 x x x x x x x 0 copy eeprom into rdac 11 1 0 0 0 0 0 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 write contents of serial register data to eeprom 12 1 0 0 1 a3 a2 a1 a0 1 x x x x x x d0 top s cale d0 = 0; normal mode d0 = 1; shutdown mode 13 1 0 0 1 a3 a2 a1 a0 0 x x x x x x d0 bottom s cale d0 = 1; e nter d0 = 0; e xit 14 1 0 1 1 x x x x x x x x x x x x software reset 15 1 1 0 0 a3 a2 a1 a0 x x x x x x x d0 software shutdown d0 = 0; normal mode d0 = 1; devic e plac ed in shutdown mode 16 1 1 0 1 x x x x x x x x d3 d2 d1 d0 copy serial register data to control register 1 x = dont care. www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 30 of 36 table 21 . address bits a3 a2 a1 a 0 potentiometer mode linear gain setting mode stored rdac memory input register rdac register input register rdac r egister 1 x 1 x 1 x 1 all channels all channels all channels all channels not applicable 0 0 0 0 rdac1 rdac1 r wb1 r wb1 rdac1 0 1 0 0 not applicable not applicable r aw1 r aw1 not applicable 0 0 0 1 rdac2 rdac2 r wb2 r wb2 rdac2 0 1 0 1 not applicable not applicable r aw2 r aw2 not applicable 0 0 1 0 rdac3 rdac3 r wb3 r wb3 rdac3 0 1 1 0 not applicable not applicable r aw3 r aw3 not applicable 0 0 1 1 rdac4 rdac4 r wb4 r wb4 rdac4 0 1 1 1 not appl icable not applicable r aw4 r aw4 not applicable 1 x = dont care. table 22 . control register bit description s bit name description d0 rdac register write protect 0 = wiper position frozen to value in eeprom memory 1 = allo w s update of wiper position through digital interface (default) d1 eeprom program enable 0 = eeprom program disabled 1 = enable s device for eeprom program (default) d2 linea r setting mode / potentiometer mode 0 = potentiometer mode (default) 1 = l inea r gain setting mode d3 burst m ode (i 2 c only) 0 = d isable d (default) 1 = enable d ( n o disable after stop or repeat start condition) www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ad5124/AD5144/AD5144a rev. 0 | page 31 of 36 rdac architecture to achieve optimum performance, analog devices, inc., has patented the rdac seg mentation architecture for all the digital potentiometers. in particular, the ad5124 / AD5144 employ a t hree - stage segmentation approach , as shown in figure 45 . the ad5124 / AD5144 / AD5144a wiper switch is designed with the transmission gate cmos topology and with the gate voltage derived from v d d and v ss . 7-bit/8-bit address decoder r l w r l a r h r h r m r m b r m r m r h r h s ts s bs 10877-048 figure 45 . ad5124 / AD5144 / AD5144a simplifie d rdac circuit top scale/bottom scale architecture in addition, the ad5124 / AD5144 / AD5144a include new position s to re duce the resistance between terminals. these positions are called bottom scale and top scale. at bottom scale, t he typical wiper resistance decreases from 130 ? to 60 ? (r ab = 100 k ? ). at top scale, the resistance between terminal a and terminal w is decre ased by 1 lsb , and the total resistance is reduced to 60 ? (r ab = 100 k ? ) . programming the vari able resistor rheostat operation 8% resistor tolerance the ad5124 / AD5144 / AD5144a operate in rheostat mode when only two terminals are used as a variable resistor. the unused terminal can be floating , or it can be tied to terminal w , as shown in figure 46 . a w b a w b a w b 10877-049 figure 46 . rheostat mode configuration the nominal resistance between terminal a and terminal b, r ab , is 10 k or 10 0 k , and has 128 /256 tap points accessed by the wiper terminal. the 7 - bit /8 - bit data in the rdac latch is decoded to select one of the 128 /256 possible wiper settings . the general equations for determining the digitally programmed output r esistance between t erminal w and t erminal b are ad5124 : w ab wb r r d d r + = 128 ) ( from 0x00 to 0x7f ( 1 ) AD5144 / AD5144a : w ab wb r r d d r + = 256 ) ( from 0x00 to 0x ff ( 2 ) where: d is the decimal equivalent of the binary code in the 7 - bit /8 - bit rdac register. r ab is the end - to - end resistance. r w is the wiper resistance . in potentiometer mode, s imilar to th e mechanical potentiometer , the resistance between t erminal w and t erminal a also produces a digitally controlled complementary resistance, r wa . r wa also gives a maximum of 8% absolute resistance error. r wa starts at the maximum resistance value and decrea ses as the data loaded into the latch increases. the general equations for this operation are ad5124 : w ab aw r r d d r + ? = 128 128 ) ( from 0x00 to 0x7f ( 3 ) AD5144 / AD5144a : w ab aw r r d d r + ? = 256 256 ) ( from 0x00 to 0x f f ( 4 ) where: d is the decimal equivalent of the binary code in the 7 - bit /8 - bit rdac register. r ab is the end - to - end resistance. r w is the wiper resistance . www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 32 of 36 if the part is configured in linear gain setting mode, the resistance between terminal w and terminal a is directly proportional to the code loaded in the associate rdac register. the general equations for this operation are ad5124 : w ab wb r r d d r + = 128 ) ( from 0x00 to 0x7f ( 5 ) AD5144 / AD5144a : w ab wb r r d d r + = 256 ) ( from 0x00 to 0xff ( 6 ) where: d is t he decimal equivalent of the binary code in the 7 - bit /8 - bit rdac register. r ab is the end - to - end resistance. r w is the wiper resistance . in the bottom scale condition or top scale condition, a finite total wiper resistance of 4 0 is present. regardless of which setting the part is operating in, limit the current between terminal a to terminal b, terminal w to terminal a, and terminal w to terminal b to the maximum continuous current of 6 ma or to the pulse current specified in table 7 . otherwise, degradation or possible destruction of the internal switch contact can occur. programming the pote ntiometer divider voltage output operation the digital potentiometer easily generates a voltage divider at wiper - to - b and wiper - to - a that is proportional to the input voltage at a to b, as shown in figure 47 . w a b v a v out v b 10877-050 figure 47 . potentiometer mode configuration connecting terminal a to 5 v and t erminal b to ground produces an output voltage at the wiper w to terminal b ranging from 0 v to 5 v. the general equation defining the output voltage at v w with respect to ground for any valid input voltage applied to terminal a and terminal b is b ab aw a ab wb w v r d r v r d r d v + = ) ( ) ( ) ( ( 7 ) where: r wb ( d ) can be obtained from equation 1 and equation 2 . r aw ( d ) can be obtained from equation 3 and equation 4 . operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. unlike the rheost at mode, the output voltage is dependent mainly on the ratio of the internal resistors, r aw and r wb , and not the absolute values. therefore, the temperature drift reduces to 5 ppm/c. terminal voltage ope rating range the ad5124 / AD5144 / AD5144a are designed with internal esd diodes for protection. these diodes also set the voltage boundary of the terminal operating voltag es. positive signals present on terminal a, terminal b, or terminal w that exceed v dd are clamped by the forward - biased diode. there is no polarity constraint between v a , v w , and v b , but they cannot be higher than v dd or lower than v ss . v dd a w b v ss 10877-051 figure 48 . maximum terminal voltages set by v dd and v ss power - up sequence because there are diodes to limit the voltage compliance at terminal a, terminal b, and terminal w ( see figure 48 ), it is important to power up v dd first before applying any voltage to terminal a, terminal b, and terminal w. otherwise, the diode is forward - biased such that v dd is powered unintentionally . the ideal power - up sequence is v ss , v dd , v logic , digital inputs, and v a , v b , and v w . the order of powering v a , v b , v w , and digital inputs is not important as long as they are powered after v ss , v dd , and v logic . regardless of the power - up sequence and the ramp rates of the power supplies, once v dd is powered, the power - on preset activate s, which restores eeprom values to the rdac registers. layout and power sup ply biasing it is always a good practice to use a compact, minimum lead length layout design. ensure that t he leads to the input are as direct as possible with a minimum conductor l ength. ground paths should have low resistance and low inductance. it is also good practice to bypass the power supplies with quality capacitors. apply l ow equivalent series resistance (esr) 1 f to 10 f tantalum or electrolytic capacitors at the supplies to minimize any transient disturbance and to filter low frequency ripple. figure 49 illustrates the basic supply bypassing configuration for the ad5124 / AD5144 / AD5144a . v dd v logic v dd v logic + v ss c1 0.1f c3 10f + c6 10f c5 0.1f + c2 0.1f c4 10f v ss ad5124/ AD5144/ AD5144a gnd 10877-052 figure 49 . power supply bypassing www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ad5124/AD5144/AD5144a rev. 0 | page 33 of 36 outline dimensions 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.20 compliant to jedec standards mo-220-wggd-8. 06- 1 1-2012- a bot t om view top view exposed pa d pin 1 indic a t or 4.10 4.00 sq 3.90 sea ting plane 0.80 0.75 0.70 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or 2.20 2.10 sq 2.00 1 24 7 12 13 18 19 6 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.05 max 0.02 nom figure 50 . 24 - lead lead frame chip scale package [l fcsp_ w q ] 4 mm 4 mm body, very very thin quad (cp - 24 - 10 ) dimensions shown in millimeters compliant to jedec standards mo-153-ac 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 coplanarity 0.10 figure 51 . 20 - lead thin shrink small outline package [tssop] (ru - 20) dimensions shown in millimeters www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 34 of 36 ordering guide model 1 , 2 r ab (k ) resolution interface temperature range package description package option ad5124bcpz10 - rl7 10 128 spi/i 2 c ? 40c to +125c 24- lead lfcsp_w q cp -24-10 ad5124bcpz100 - rl7 100 128 spi/i 2 c ? 40c to +125c 24- lead lfcsp_wq cp -24-10 ad5124bruz10 10 128 spi ? 40c to +125c 20- lead tssop ru -20 ad5124bruz100 100 128 spi ? 40c to +125c 20- lead tssop ru -20 ad5124bruz10 - rl7 10 128 spi ? 40c to +125c 20- lead tssop ru -20 ad5124bruz100 - rl7 100 128 spi ? 40c to +125c 20- lead tssop ru -20 AD5144bcpz10 - rl7 10 256 spi/i 2 c ? 40c to +125c 24- lead lfcsp_wq cp -24-10 AD5144bcpz100 - rl7 100 256 spi/i 2 c ? 40c to +125c 24- lead lfcsp_wq cp -24-10 AD5144bruz10 10 256 spi ? 40c to +125c 20- lead tssop ru -20 AD5144bruz100 100 256 spi ? 40c to +125c 20 - lead tssop ru - 20 ad5 144bruz10 - rl7 10 256 spi ? 40c to +125c 20- lead tssop ru -20 AD5144bruz100 - rl7 100 256 spi ? 40c to +125c 20- lead tssop ru -20 eval - AD5144dbz evaluation board AD5144abruz10 10 256 i 2 c ? 40c to +125c 20- lead tssop ru -20 AD5144abruz100 100 256 i 2 c ? 40c to +125c 20- lead tssop ru -20 AD5144abruz10 - rl7 10 256 i 2 c ? 40c to +125c 20- lead tssop ru -20 AD5144abruz100 - rl7 100 256 i 2 c ? 40c to +125c 20- lead tssop ru -20 1 z = rohs compliant part . 2 the evaluation board is shipped with the 10 k? r ab resistor option; however, the board is compatible with both of the available resistor value options. www.datasheet.net/ datasheet pdf - http://www..co.kr/
data sheet ad5124/AD5144/AD5144a rev. 0 | page 35 of 36 notes www.datasheet.net/ datasheet pdf - http://www..co.kr/
ad5124/AD5144/AD5144a data sheet rev. 0 | page 36 of 36 notes i 2 c refers to a communications proto col originally developed by philips semiconductors (now nxp semiconductors). ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners . d10877 - 0- 10/12(0) www.datasheet.net/ datasheet pdf - http://www..co.kr/

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